As the number of functional cores integrated on a single chip has exceeded 10, 20, and beyond, the post-silicon visibility of crucial inter-core signals has diminished often to zero.  This has caused the time taken to validate the SoC to stretch to over a quarter of the overall development time*.

ClearBlue provides the SoC design engineer not only the visibility of deeply embedded signals to find and isolate functional bugs, but the ability to control those signals and to even work around those bugs in-silicon.

• Visibility of simulation-based validation post-silicon, at-speed
• The ability to fix isolated bugs without using FIB’s or going back through the fab
• Unified pre- and post-silicon validation environment