DAFCA's ClearBlue Silicon Validation Platform is a design automation system for use in post silicon validation. It provides a comprehensive suite of post silicon applications designed to reduce the time between first silicon availability and volume production. ClearBlue is composed of an extensive set of applications designed to accelerate first silicon bring-up, ease hardware and software integration, enable in-silicon performance monitoring, and in general, provide a comprehensive platform for inspection and diagnosis of on-chip, at-speed behavior.

Only through the application of innovative validation solutions will companies reduce the time for post-silicon development and related expenses associated with delayed product release. Development of nano-era SoC devices necessitates superior tools that allow teams to not just observe circuit behavior but subject circuits to stress and fault conditions, allowing the early discovery and diagnosis of integration problems, configuration problems, and unexpected behaviors resulting from functional, signal integrity, power, or process related issues.

DAFCA's ClearBlue solution enables the discovery of such problems and facilitates an understanding of how such problems manifest themselves functionally. Most importantly, ClearBlue can help isolate the scope of such problems, allowing silicon bring-up teams to more narrowly focus time and expense for root cause identification and resolution. Below is a brief description of the major components of ClearBlue Silicon Validation Platform.

ClearBlue Instrumentation Studio

Instrumentation is performed on a synthesizable Verilog or VHDL design using ClearBlue Instrumentation Studio. A design engineer or system integrator analyses the design, selects strategic points and then inserts the desired instrument structures to be used post-silicon.

Once complete, ClearBlue Instrumentation Studio produces the RTL of the instrumented design to be taken through a standard ASIC design flow to production.

ClearBlue Instrumentation Studio generates scripts to easily interoperate with other commercially available EDA products. For instance, it generates a script for Conformal to verify that the user design has not been altered by the instrumentation.

ClearBlue Silicon Validation Studio

After fabrication of the chip, ClearBlue Silicon Validation Studio employs the on-chip instruments to provide visibility and control of the instrumented signals. In particular, ClearBlue Silicon Validation Studio is used to:

• Configure the instruments to perform validation, monitoring, acquisition, stimulus, fault injection and debug functions at-speed
• Extract at-speed data from instrumented signals
• Display the extracted data within popular tools such as Debussy, Verdi, and simulators such as NC-Sim and VCS
• Automatically run in-silicon assertions as part of system regressions
• Automatically run sophisticated sequences of observability, control and performance monitoring functions.
• Automatically generate data acquisition, performance monitoring and system regression reports

Applications provided with the tool include:

• Logic Analysis
• Logic Stimulus and Fault Insertion
• Assertion Based Debug
• Event Analyzer
• Performance Monitoring

ReDI Library

ClearBlue Silicon Validation Studio is built upon the manipulation and utilization of the ReDI (Reconfigurable Distributed Infrastructure) instruments integrated on-chip.

Following is a sample list of ReDI instruments that can be inserted into the user design. All instruments are customized and inserted at design time:

• Signal Probe Network (SPN) -- a configurable set of multiplexors with integrated configuration registers, pipeline registers and FIFOs.
• Programmable Trigger Engine (PTE) -- a programmable state machine used for creating onchip assertions, triggers and performance monitoring functions.
• rWRAP / Reconfigurable Logic Engine (RLE) -- a reconfigurable logic block used as a wrapper (rWRAP) or as a shared resource (RLE) resource for assertions, triggers, counters, comparators, generators or other user defined logic functions.
• Tracer -- a trace buffer memory management block used in conjunction with user defined memories and the PTE or RLE for on-chip capture data
• CapStim -- similar to the Tracer but with additional ability to extract stimulus vectors from embedded memory, also used in conjunction with the PTE or RLE.
• Debug Module -- Alias for an instrument set composed of a combination of PTE and/or RLE with Tracer or CapStim

All instruments placed in the design are configured and controlled via the Instrument Access Mechanism, a simple extension to the JTAG TAP, which is automatically generated by ClearBlue Instrumentation Studio.